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摘要: 介绍了I2C总线协议及基于FPGA芯片的I2C总线接口结构框图.提出了复杂时序电路状态机嵌套的设计思想,并给出了基于Verilog HDL的I2C总线接口电路的硬件描述.在ISE 6.1i平台下结合ModelSim SE 5.7进行了设计仿真,实现了XC2S100对I2C总线器件的读写操作.
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关键词:
- 现场可编程门阵列(FPGA) /
- XC2S100 /
- I2C总线 /
- Verilog HDL /
- 状态机嵌套
Abstract: The protocol and principle of I2C-Bus were introduced. The framework of I2CBus based on FPGA was proposed. The idea of nesting state-machine of complicated timing-circuit and the hardware description of I2C-Bus interface by Verilog HDL were presented. The simulation of designing under the Xilinx ISE 6.1i development platform combined with ModelSim SE 5.7 was made and the operation on I2C device based on Spartan II XC2S100 was implemented.
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