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LEI Jian-hong, JING Zhi-cheng, SHEN Jian-guo. The Timing Problem of Synchronous Design in FPGA/CPLD[J]. Journal of East China Normal University (Natural Sciences), 2004, (3): 66-70,9.
Citation:
LEI Jian-hong, JING Zhi-cheng, SHEN Jian-guo. The Timing Problem of Synchronous Design in FPGA/CPLD[J]. Journal of East China Normal University (Natural Sciences), 2004, (3): 66-70,9.
LEI Jian-hong, JING Zhi-cheng, SHEN Jian-guo. The Timing Problem of Synchronous Design in FPGA/CPLD[J]. Journal of East China Normal University (Natural Sciences), 2004, (3): 66-70,9.
Citation:
LEI Jian-hong, JING Zhi-cheng, SHEN Jian-guo. The Timing Problem of Synchronous Design in FPGA/CPLD[J]. Journal of East China Normal University (Natural Sciences), 2004, (3): 66-70,9.
This paper discusses the timing problem in FPGA/CPLD design. It digs out the reasons of this kind of problem and the influence of them on design. Finally, it concludes with some resolutions for the timing design.